This invention relates generally to integrated circuits (ICs) and, more particularly, to a design of ICs with tub-ties and shallow trench isolation (STI) and to a process for making them.
In conventional CMOS (complementary metal oxide semiconductor) technology NMOS transistors are embedded in a p-type tub (or well), and, conversely, PMOS transistors are embedded in an n-type tub (or well). Each tub serves to isolate the transistors therein from the bulk substrate and from transistors in the other tub. However, the tubs should not be left floating; i.e., they should be connected to either Vcc or to ground in order to prevent latch-up. For this purpose special conducting paths, known as tub-ties, establish ohmic connections between appropriate metal layers (the tub-tie contacts) and each of the tubs. Not every transistor needs a tub-tie, but every tub needs at least one tub-tie. Typically, the area of a tub-tie at the surface of the semiconductor is relatively small, measuring only about 1 xcexcmxc3x971 xcexcm. In LOCOS (local oxidation of silicon) isolation the tub-tie is formed in zones of silicon located between regions of isolating field oxide (FOX) when viewed in cross-section, whereas in STI (shallow trench isolation) it is formed in small pillars of silicon disposed between isolating oxide-filled trenches when viewed in cross-section.
In standard CMOS front-end processing (i.e., processing up to but not including metalization), which usually entails about ten different photolithographic mask steps to fabricate the transistors, the source/drain (S/D) regions are typically doped heavily, whereas the tubs are only lightly doped. The tub-tie regions are also heavily doped, usually during the same ion implantation step that dopes the S/D regions. Doping of the n-type tub-tie region of the PMOS transistors, for example, is accomplished by opening a hole over the tub-tie location in the photoresist (PR) mask that protects the PMOS transistor locations during the n-type ion implantation of the S/D regions of the NMOS transistors. Conversely, doping of the p-type tub-tie region of the NMOS transistors is accomplished by opening a hole over the tub-tie location in the PR mask that protects the NMOS transistor locations during the p-type ion implantation of the S/D regions of the PMOS transistors.
However, IC fabrication processes that require a large number of PR mask steps are undesirable, in general implying lower yields and higher cost than processes that utilize fewer PR mask steps. Consequently, workers in the IC art have endeavored to reduce the number of PR mask steps required. See, for example, T. Horiuchi, U.S. Pat. No. 5,571,745 issued on Nov. 5, 1996, U. Schwalke et al., European Solid-State Device Research Conference, Conf. Proc., pp. 317-320 (1996), and U. Schwalke et al, Symposium On VLSI Technology, Digest of Technical Papers, pp. 71-73 (1997). While the various prior art implementations differ, they all accomplish PR mask reduction by combining two or more implant steps, such as tub implants with gate implants. The most aggressive approach, which entails the largest cost reduction, combines all implants into a single PR mask step. However, in so doing the PR mask previously utilized to allow selective doping of the tub-tie regions is no longer available. We addressed the problem of reducing mask-count yet enabling tub-tie regions to be formed in U.S. Pat. No. 5,949,112 issued to us on Sep. 7, 1999 (hereinafter the Gossmann-Vuong patent), which is incorporated herein by reference.
The Gossmann-Vuong patent describes the structure of an IC that comprises a tub of a first conductivity type, at least one transistor embedded in the tub, and a first pair of isolating regions defining therebetween a tub-tie region coupled to the tub. The tub-tie region comprises a cap portion of the first conductivity type and an underlying buried pedestal portion of a second conductivity type. At least a top section of the pedestal portion is surrounded by the cap portion so that a conducting path is formed between the cap portion and the tub. In a CMOS IC an n-type tub tie of this design is provided for PMOS transistors in n-type tubs, and a p-type tub-tie of this design is provided for NMOS transistors in p-type tubs. In a preferred embodiment, the cap portion of each tub-tie comprises a relatively heavily doped central section and more lightly doped peripheral sections, both of the same conductivity type.
The Gossmann-Vuong patent also describes a reduced-mask-count process for making CMOS ICs. The process includes forming the isolating regions so that each has a protrusion which extends over the surface regions where the peripheral sections of the cap portion are to be formed. Then, a combination of ion implantation energies and concentrations, as well as suitable PR masking, in conjunction with the shape of the isolating regions, enables selective doping of the pedestal portion and the cap portion (central and peripheral sections). Illustratively, the isolating regions are FOX regions formed by a LOCOS process or TROX (trench oxide) regions formed by an STI process.
In the STI process described in the Gossmann-Vuong patent, FIG. 9B (FIG. 1B herein) shows that the isolating regions 120 and 122 have reduced-thickness protrusions 120.1 and 122.1, respectively, that extend over the peripheral sections 161.1 of the tub-tie. Ion-implantation is performed to produce the various regions of the tub-tie (as well as the source/drain/extensions etc.). The direction of these implantation steps is perpendicular to the top surface of the IC wafer. Although this approach is a considerable advance over prior art techniques, there is still room for improvement in several areas: first, formation of the protrusions 120.1 and 122.1 requires an extra photolithographic masking step; second, tight control of mask alignment is required to avoid pinch-off; i.e., in the case of a p-type tub-tie, avoiding an n-type conducting path between the n-type pedestal portion 162 and the isolation regions 120 and 122, and vice-versa; and third, the tub-tie pedestal portions 152 and 162 are electrically floating and hence tend to accumulate charge that can result in an unpredictable transient behavior of the IC.
Thus, a need still remains in the art of making IC tub-ties for a further reduced-mask-count STI IC process.
A need also remains for such a process, and corresponding tub-tie design, that decreases the likelihood of pinch-off of the tub-tie.
In addition, a need remains for such a process, and corresponding tub-tie design, that reduces charge build-up in the pedestal regions.
In accordance with one aspect of our invention, a method of fabricating an IC comprises the steps of: (a) forming trench isolation regions in a surface of a semiconductor body; and (b) forming a tub-tie region between at least one pair of the trench isolation regions (when viewed in cross-section) by a process that includes the following steps: (b1) forming a first photolithographic mask that covers and is in registration with the tub-tie region; (b2) implanting ions of a first conductivity-type to form a tub region adjacent the tub-tie region; (b3) removing the first mask; (b4) forming a second photolithographic mask that has an opening that exposes most of the underlying tub-tie region but overlaps a first peripheral section on one side of the tub-tie region; (b5) implanting ions to form a pedestal portion of a second conductivity-type within the tub-tie region; (b6) implanting ions of the first conductivity-type at an acute (preferably non-zero) angle xe2x88x92xcex1 with respect to the normal to the surface to the body so as to form a first conductivity-type localized first zone that extends into the first peripheral section; and (b7) forming an electrode in contact with the tub-tie region.
In a preferred embodiment, the first conductivity-type tub of step (b2) and the second conductivity-type pedestal of step (b5) are formed by implanting ions at an acute (non-zero) angle +xcex2 to the normal to the surface of the body.
In yet another embodiment, between steps (b1) and (b3) ions of the second conductivity type are implanted at an acute angle xe2x88x92xcex1 to the normal to said surface so as to form a second conductivity-type, highly doped localized second zone that extends into a second peripheral region so as to make ohmic contact between the electrode and the pedestal portion.
In accordance with another aspect of our invention, an integrated circuit comprises: a tub of a first conductivity type disposed in a semiconductor body having a top major surface, at least one transistor embedded in the tub, a pair of shallow trench isolating regions, and a tub-tie region disposed between the isolating regions when viewed in cross-section. The tub-tie region includes a cap portion and an underlying pedestal portion of a second conductivity type. The cap portion contacts at least a top section of the pedestal portion and has at least a section of the first conductivity type that forms a conducting path between the cap portion and the tub, characterized in that the pedestal portion is oriented at approximately an acute (non-zero) angle +xcex2 to the normal to said surface, and the cap portion includes a highly doped peripheral first zone of the first conductivity type located adjacent a portion of one of said isolating regions. The peripheral first zone reduces the likelihood of pinch-off.
In another embodiment of this aspect of our invention, the cap portion includes a highly doped peripheral second zone of the second conductivity type located adjacent a different portion of one of the isolating regions. The second peripheral zone prevents any significant amount of charge build-up in the pedestal portion.